The function of a phase multiplier circuit is to generate equal-frequency output signals, each having a phase, from an input signal. In one embodiment, the phases of the output signals are evenly spaced between 0 and 360 degrees.
FIG. 1 is a schematic diagram illustrating an example of a phase multiplier of the prior art. This circuit is commonly referred to as a delay-locked loop. A voltage-controlled delay line 2 is coupled to an input signal IN and is comprised of five voltage-controlled delay subcircuits U1, U2, U3, U4, and U5, and has four outputs: OUT1, OUT2, OUT3, and OUT4.
Also included in FIG. 1 is a phase detector 3, a charge pump 4, a loop filter capacitor C1, a reset transistor M3, a reset inverter U12, and a reset synchronization flip-flop U10. The phase detector includes flip-flops U6 and U7, AND gate U8, and OR gate U9. The charge pump includes transistors M1 and M2, and inverter U11. The voltage of a CONTROL node controls the delay though the delay subcircuits. Coupled to the CONTROL node is the charge pump, the loop filter capacitor, and the voltage controlled delay line.
Initially, the delay-locked loop is reset by asserting RESET high. In this state, the voltage of the CONTROL node is set to AVDD, forcing the delay through the delay line to a minimum, and the phase detector is also reset. Through action of U10, phase detector reset signal RESETX is synchronous to the rising edge of IN. Subsequent to the falling edge of RESET, RESETX must fall immediately after the rising edge of IN but before the rising edge of FB. D flip-flop U10 ensures that this occurs by synchronizing RESETX to the rising edge of IN.
After RESET is deasserted low, and by adjusting the voltage of the CONTROL node in a negative feedback loop, the delay-locked loop increases the delay of the delay line until the phase of FB is equal to the phase of OUT1. It then follows that the phases of the output signals are equally spaced about 360 degrees, but only if the delay subcircuits are well matched, and the phase error between FB and OUT1 is zero. These two requirements to achieve equal spacing can be difficult to meet. By eliminating the phase detector and by measuring and adjusting the delays of delay subcircuits individually, the present invention effectively eliminates these requirements for equal phase spacing.